A5s 网络摄像机芯片采用528MHz ARM11处理器,高清H.264和MJPEG视频编码引擎,并且集成了强大的图像处理单元。A5s 网络摄像机芯片拥有多通道视频编码器,支持高达14MP像素的视频编码,先进的3D MCTF 降噪技术和宽动态处理功能,支持多达四路的视频流(其中两路视频流可达1080p30+800x600p30)。
45纳米芯片工艺及丰富的I/O设备,将A5s的eBOM缩减到最小,可让产品适用于多样化的外形,例如:自动对焦的枪型摄影机、微型球机以及袖珍无线摄像机等。A5s网络摄像机解决方案是以Linux系统为基础的软件开发包,提供丰富多样的ARM层API以满足不同差异化需求和性能优化。

Ambarella A5s Block Diagram

Ambarella A5s Block Diagram

Overview
The A5s IP Camera SoC integrates powerful image sensor processing, HD 1080p30 H.264 multi-stream encoding, and an ARM11 processor with rich I/O for IP Camera and Network Video Server (NVS) applications. Leveraging Ambarella’s technology leadership in professional broadcasting, A5s offers excellent video quality, 3D noise reduction, digital WDR and four independent H.264/MJPEG streams.
The A5s SDK supports development of fully-featured IP Cameras and multi-channel NVS devices while offering developer differentiation such as analytics, digital PTZ, customizable AWB/AE/AF and a wide range of sensor choices.

Key Features
Single Platform, Many Uses
° From entry-level SD to high-end multi-megapixel
° Wide range of sensors supported
Promotes Differentiation
° High-performance, software-programmable
° Proven Linux SDK and rich ARM-level APIs
Cost And Power Efficient
° Ultra-compact BOM with a single 16-bit DDR
° Less than 3 Watts for a complete camera design
Superior Image Quality
° Advanced image sensor pipeline
° 3D noise reduction
Enhanced Video Processing
° Digital WDR
° AE/AWB/AF, digital PTZ, face tracking, more
State-Of-The-Art H.264 Compression Engine
° High compression ratio, also in high motion scenes
° Full HD 1080p30 + D1

General Specifications
Sensor and Video I/O
° 8-lane SLVDS, HiSPI™, MIPI CSI-2, and parallel
° Up to 14 Mpixel resolution and 240 MHz pixel rate
° BT.656/1120 108 MHz 1-4 ch video input/output
° HDMI 1.3 out
Front End Sensor Processing
° Lens correction
° Black level correction
° Defect pixel cluster correction
° CFA crosstalk noise filtering
° RGB Bayer demosaicing
° 3D color transformation with gamma
Image Processing
° 3D noise reduction filtering
° Digital WDR contrast enhancement
° AE/AWB/AF libraries supplied
° Day/Night and DC/Stepper iris control
° Flicker suppression
° Alpha-blending OSD; text, overlays, privacy mask
° Digital WDR contrast enhancement
° Crop, mirror, flip, scale, digital PTZ
° Saturation, brightness, contrast
° Motion and face detection
Low Power
° 650 mW power consumption for 1080p30 encode
Video Encoder
° H.264 BP/MP/HP Level 5.0
° MJPEG
° Up to 4 simultaneous streams
° Up to 14MP resolution
° Full HD 1920x1080@30fps + D1
° 3MP@20fps, 5MP@12fps, or 10MP@3fps
° CBR/VBR/ConstantQP rate control
CPU
° 528 MHz ARM1136J-S
° AES/DES/3DES cryptographic acceleration
Memory
° 1x 16-bit DDR2/DDR3/Mobile DDR/Mobile DDR2
Peripherals
° SDIOx2 for SD Card and 3G/WiFi
° Ethernet MII
° USB 2.0 Device
° I2S audio in/out
° NAND Flash, 16-bit Host i/f
° SSI/SPI, IDC, PWM, GPIO, RS-232C/485
° Real-time clock, watchdog timer, JTAG
Physical
° 15x15 mm, 404 pin TFBGA package
° Operating temperature: -20˚C to +85˚C

A7 网络摄像机芯片是安霸的旗舰级网络摄像机解决方案。 它集成了最先进的五亿像素每秒的图像处理通路、多路视频编码引擎,可做到H.264/MJPEG的1080p60编码, 并包含一个ARM11的CPU。

A7 旨在打造支持多路高清功能的高性能网络摄像机,它能支持高达三千两百万像素,并且拥有动态补偿的3D降噪功能,以及广播级质量的H.264编码器, 可同时做8路独立编码。

Ambarella A7 Block Diagram

Ambarella A7 Block Diagram

Overview
The Ambarella A7 is a high performance IP Camera SoC that integrates a powerful image sensor pipeline and a multi-streaming, high quality, 1080p60 H.264 encoder and an ARM CPU.
Tuned for surveillance applications, the A7 leverages Ambarella’s professional broadcast encoding technology with advanced 3D noise reduction to deliver pristine video at exceptionally low bit rates, even in complex high-motion and low-light scenes.
The industry-proven Linux SDK offers IP Camera vendors a high degree of differentiation through a rich API set with access to functions such as 3A tuning, digital PTZ, and dynamic range enhancements, while offering a predictable, fast path to production.

Key Features
Broadcast-Grade 1080p60 H.264 Codec
°Low power, simultaneous 1080p60 + VGA H.264 encoding
° Multi-streaming with on-the-fly changes of frame rate, bit rate, and GOP structure
°Exceptionally low bit rates also in high-motion scenes
High-Performance ISP
° 500 MHz pixel capture rate equivalent to 8 MP at 60 fps
° Up to 32 MP sensor resolution
Advanced Image Processing
° Motion compensated 3D noise reduction delivers smear-free video (MCTF)
° Digital WDR contrast enhancement and tone mapping
°Multi-window digital PTZ
Flexible, Low Power SoC Platform
° ARM11 and DSP subsystem
° Linux-based SDK with rich API set provides for vendor differentiation
° 1.5 Watt for 1080p60 encode
General Specifications
Sensor and Video I/O
° 12-lane SLVDS, HiSPI™ and parallel interface
° 500 MHz pixel capture rate, 32 MPixel sensor support
° BT.601/656/1120 YUV video in
° Dual digital video out; HDMI, BT.656/1120, RGB
° Composite video out
Front End Sensor Processing
° Lens shading and chromatic aberration correction
° Black level correction
° Barrel compensation
° Defect pixel cluster correction
° CFA crosstalk and fixed pattern noise filtering
° RGB Bayer demosaicing
° 3D color transformation with gamma
Image Processing
° 3D motion-compensated noise reduction (MCTF)
° Digital WDR contrast enhancement
° AE/AWB/AF libraries supplied
° Day/Night and DC/Stepper iris control
° Flicker suppression
° Four independent resizers with digital PTZ
° Crop, mirror, flip, 90 degree rotation
° Alpha-blending OSD; text, overlays, privacy mask
° Video warp engine
Low Power
° 1.5 W power consumption for 1080p60 encode
Video Encode
° H.264 BP/MP/HP Level 5.1, up to 1080p60+VGA
° Encode of 4MP@30fps, 5MP@24fps, 10MP@10fps
° MJPEG - over 200 Mpixels/s
° Up to 32 Megapixel encode resolution
° Broadcast-grade ME; up to 1920 pel search range
° Dynamic GOP, intra refresh, IDR insertion
° Sub-frame low-delay encoding
° CABAC up to 50 Mbps, CAVLC up to 100 Mbps
° Multi-streaming with on-the-fly changes of frame rate, bit rate, resolution, and GOP
° CBR, VBR, and Capped VBR with quality/fps priority
CPU
° 528 MHz ARM1136J-S CPU
° AES/3DES/SHA-1/MD-5 hardware crypto engine
Memory
° 32-bit DDR2/LPDDR2/DDR3/DDR3L, 384 MHz
Peripherals
° SMIO controller for NAND, SDIO (2), CF, MMC, IDE
° Dual Ethernet MII and USB 2.0 Device
° I2S (6), SSI/SPI (3), IDC (3), PWM (5), RS-232C/485 (2)
° GPIO (up to 155), Stepper motor (4 sets), ADC (6 ch)
° Host interface (Intel/Motorola), RTC, WDT, JTAG
Physical
°15x15 mm, 528 ball FPGA package
° Operating temperature: -20˚C to +85˚C